Silicon germanium (SiGe) epitaxial layers formed on silicon (Si) wafers have been extensively investigated because they enable the passivation of interfaces and the generation of devices with diverse functions. For example, the heterostructure of SiGe on Si may be used to form a heterojunction bipolar transistor. Another example is an epitaxial layer of SiGe formed on source and drain regions of an MOS transistor for reducing the resistance of the source and drain regions.
Generally, SiGe epitaxial layers are formed with patterns instead of as a blanket on a Si wafer. A selective low pressure chemical vapor deposition (LPCVD) process is often performed to selectively grow SiGe epitaxial layers. FIG. 1 shows a Si wafer 100 having SiGe selectively formed thereon. To form the structure shown in FIG. 1, a Si wafer 100 is first provided. A plurality of patterns 102 are formed on Si wafer 100, exposing portions of Si wafer 100. Patterns 102 may comprise a layer of dielectric or otherwise may be capped with dielectric. Si wafer 100 having patterns 102 formed thereon is cleaned with hydrofluoric acid to remove native oxide on the exposed portions of Si wafer 100 and then sent to a CVD (chemical vapor deposition) machine. After Si wafer 100 is loaded into the CVD machine, another cleaning step is performed by baking Si wafer 100 in a hydrogen (H2) environment. A selective epitaxial growth by LPCVD is then performed to deposit a layer of SiGe 104 on the exposed portions of Si wafer 100. In particular, the LPCVD process uses a source gas including dichlorosilane (SiH2Cl2, also “DCS”), germane (GeH4), H2, and hydrochloride (HCl), where DCS and GeH4 are the respective source gases for silicon and germanium, H2 is the carrier gas for diluting DCS and GeH4, and HCl acts as an etchant gas. In the source gas, a flow rate of DCS is approximately 40-80 sccms (standard cubic centimeter per minute, a flow rate of GeH4 is approximately 100 sccms to several hundred sccms, a flow rate of HCl is approximately 100 sccms and above, and a flow rate of H2 is on the order of several to tens of slms (standard liters per minute). Because patterns 102 comprise dielectric or are capped with dielectric, SiGe is formed only on the exposed portions of Si wafer 100.
A pattern dependence problem with the above selective LPCVD process refers to a phenomenon that the quality of SiGe layer 104 depends on a dimension of the exposed portions of the Si wafer. In particular, because SiGe and Si have different lattice constants, SiGe formed on a Si substrate is susceptible to the effect of defects on a surface of the Si substrate, especially on small surface areas of the Si substrate. Consequently, the selective LPCVD process may succeed in manufacturing large devices but may fail in manufacturing small devices. For example, using the same selective LPCVD process, the yield of manufacturing devices having a critical dimension of 90 nm may be significantly higher than the yield of manufacturing devices having a critical dimension of 65 nm.
Another problem with the above selective LPCVD process is sometimes referred to as the mushroom problem and may be described with reference to FIG. 2, which shows a specific example of the structure of FIG. 1. As shown in FIG. 2, one of patterns 102, labeled as 102-1, comprises a gate structure of an MOS transistor 10, where MOS transistor 10 also includes two diffusion regions 106 and 108 formed in Si wafer 100 as source and drain regions. Pattern 102-1 comprises a layer of gate dielectric 110, a gate electrode 112 comprising polysilicon, a cap layer 114 comprising an oxide or nitride, and two spacers 116 on sidewalls of gate electrode 112 and gate dielectric 110. SiGe layers 104 are deposited by the selective LPCVD process on diffusion regions 106 and 108 to thicken the source and drain regions of MOS transistor 10, thereby reducing a resistance of the source and drain regions. Diffusion regions 106 and 108 may also be recess etched, as shown in FIG. 2, so that SiGe layers 104 are partly formed on the sides of a channel region between diffusion regions 106 and 108 for improved carrier mobility in the channel. It is generally desirable that cap layer 114 cover the entire surface of gate electrode 112 such that no SiGe is formed on gate electrode 112. However, it is possible or sometimes necessary that a part (as shown in FIG. 2) or a whole (not shown) of gate electrode 112 is exposed when the selective LPCVD process is performed. As a result, polycrystalline SiGe forms on the exposed portion of gate electrode 112. Although HCl used in the LPCVD process etches polycrystalline SiGe as it grows, the etching rate of polycrystalline SiGe depends on a flow rate of HCl. If the flow rate of HCl is not sufficiently high, a residue 104′ of the polycrystalline SiGe remains on the exposed portion of gate electrode 112. Because the polycrystalline SiGe also expands laterally, polycrystalline residue 104′ is often in the shape of a mushroom.
The mushroom problem may be suppressed by increasing the flow rate of HCl so that polycrystalline SiGe is etched at a faster speed. However, because HCl also etches crystalline SiGe, as the flow rate of HCl increases, a growth rate of SiGe decreases and a quality of crystalline SiGe formed on the source and drain regions of MOS transistor 10 is degraded.